AMD K5 Manual de usuario

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xAMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION

For more information or to order literature,write to or call:TOLL FREE: (800)222-9323(512)602-5651 Advanced Micro Devices, Inc.5204 East Ben White Blv

118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION1 AMD-K5™ Processor Features Four-issue superscalar core with six parallel execut

2AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION1.2 High-Performance DesignThe superscalar RISC design techniques provide next-gen

318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONRevision HistoryDate Revision DescriptionJan. 1997 FThe PR166 OPN added to Orderin

4AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION2 Block DiagramFetchDecodeLoadStoreExecute8 Ports64ResultRetireFastpath Hardware R

518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION3 Ordering InformationStandard ProductsAMD standard products are available in seve

6AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION4 Architectural IntroductionThe x86 architecture is the dominant standard for the

718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONunit can operate independently, other units can continue exe-cution when one or mo

8AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONcessor’s high performance. In addition to indicating where the x86 instruction beg

918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONa given memory location returns valid data. Each cache line is assigned one of the

© 1997 Advanced Micro Devices, Inc. All Rights Reserved.Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes inits produc

10AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONAt the beginning of the decode process, the decoder scans the x86 instructions an

1118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONresults, recover from mispredictions and exceptions, and hold the relative specul

12AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION5 CPU IdentificationUpon completion of RESET, the DX register contains a componen

1318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION6 Logic Symbol DiagramA20MA31–A3APADSADSCAPCHKBE7–BE0AHOLDBOFFBREQHLDAHOLDD/CEWBE

14AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION7 Signal DescriptionsA31–A5/A4–A3 Address Lines Input/OutputA31–A3 are used with

1518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONAP Address Parity Input/OutputThe AP signal provides even parity for the addres

16AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONBF1–BF0 (Model 1 and Model 2)Bus Frequency InputFor the AMD-K5 model 1 and model

1718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONthe drive strength is strong. The A31–A22 signals use the weak drive strength at

18AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIOND63–D0 Data Lines Input/OutputThe D63–D0 signals are the 64-bit data bus. These s

1918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFLUSH Cache Flush InputAsserting FLUSH will flush the internal caches. For accep

iii18522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONContents1 AMD-K5™ Processor Features . . . . . . . . . . . . . . . . . . . . .

20AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONHOLD Bus Hold Request InputThe HOLD signal is used to request the processor bus.

2118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONINV Invalidation InputThe INV signal is used to designate the MESI protocol stat

22AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONPCD Page Cache Disable OutputThe PCD signal provides cacheability status by repo

2318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONR/S Run/STOP InputThe R/S signal provides an edge-sensitive interrupt to stop nor

24AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONTMS Test Mode Select InputThe TMS signal is used to select the TAP Test modes. Th

2518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONCLK Clock PEN Synchronous Note 4EADSSynchronous RESET AsynchronousEWBESynchronous

26AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONTable 3. Input/Output PinsName When FloatedA31–A5 Bus Hold, Address Hold, BOFFAP

2718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONTable 6. Special CyclesSpecial Cycle A4 BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 M/IO D/C

28AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION8 Processor Operation8.1 Power-On ConfigurationThe AMD-K5 processor signals at re

2918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 3. State Transition Diagram for Stop Clock State MachineEADSEADSUpon com

ivAMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONDP7–DP0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONNormal Execution StateIn this state, the AMD-K5 processor operates at full speed.

3118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONinterrupt, or maskable interrupt), recognition of STPCLK is delayed until the int

32AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONThe AMD-K5 processor uses the MESI protocol—2 bits per cache line—in its data cac

3318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONThe INVD instruction invalidates the entire cache and gener-ates a Flush special

34AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONthe new line is received, it is forwarded to the execution units. When all four q

3518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONread cycle as shown in Table 8. The final state of the data cache line is determi

36AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONInstruction Cache CoherencyThe instruction cache protocol is a subset of the data

3718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 4. Bus State TransitionsMemory OrganizationPhysical memory address space

38AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONMemory objects can be 8, 16, 32, or 64 bits. I/O objects are 8, 16, or 32 bits. B

3918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONSingle Transfer CyclesSingle transfer cycles are initiated with the assertion of

v18522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONInternal Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONthe external memory system is ready to receive data adds addi-tional wait states,

4118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONwhile the data cycle continues. Assertion of HOLD can occur at any time, but HLDA

42AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONLocked Operations A locked cycle, illustrated in Figure 8, uses the LOCK pin to i

4318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONThe LOCK pin is asserted for the duration of locked accesses. Note also that at l

44AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 9. HOLD/HLDA CycleHLDA is negated one clock after HOLD is negated. Hold

4518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONInterrupt AcknowledgeAn interrupt acknowledge cycle, shown in Figure 10 on page 4

46AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 11. Inquire Cycle (Hit to a Non-Modified Line)Figure 12. Inquire Cycle

4718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONPipelining The following pipeline cycles are supported by AMD-K5 pro-cessors mode

48AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONPipelining is not supported for the following cycles: Non-cacheable instruction

4918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONPipelining Timing DiagramsThe timing diagrams in Figure 13 and Figure 14 illustra

viAMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION10 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .

50AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 14. Pipelined Write Cycle (Could be I/O) into a Write Cycle (Could be I/

5118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION8.7 System Management ModeSystem Management Mode (SMM) is a distinct processor mo

52AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONTable 12. SMM Save Area MapAddress Contents Address ContentsFFFCh CR0 FF74h LDT A

5318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONInitial State Upon Entering SMMTable 13 shows the initial state of the processor

54AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONunpredictable if the I/O instruction restart word is written when the processor h

5518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION Adds the EWBE input to indicate an empty external write buffer (This supports s

56AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION9 Electrical Data9.1 Power and GroundingPower Connections The AMD-K5 processor in

5718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION9.2 Absolute Maximum Ratings Case Temperature under Bias...

58AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONTable 14. DC Characteristics over Commercial Operating RangesSymbol Parameter Des

5918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION10 Switching CharacteristicsThe AMD-K5 processor commercial switching characteris

vii18522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONList of FiguresFigure 1. Block Diagram . . . . . . . . . . . . . . . . . . . .

60AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONTable 16. Delay Timing for 66-MHz Bus OperationSymbol Parameter DescriptionAdvanc

6118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONTable 17. Switching Characteristics for 66-MHz Bus OperationSymbol Parameter Desc

62AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION10.2 60-MHz Bus OperationTable 18. CLK Switching Characteristics for 60-MHz Bus O

6318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONTable 20. Switching Characteristics for 60-MHz Bus OperationSymbol Parameter Desc

64AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION10.3 50-MHz Bus OperationTable 21. CLK Switching Characteristics for 50-MHz Bus O

6518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONTable 23. Switching Characteristics for 50-MHz Bus OperationSymbol Parameter Desc

66AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION10.4 RESET, TCK, TRST, and Test Signal TimingTable 24. RESET Configuration Signal

6718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONTable 26. Test Signal Timing at 16 MHzSymbol Parameter DescriptionAdvance InfoFig

68AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 15. Diagrams KeyFigure 16. CLK WaveformMust besteadyMay changefrom Hig

6918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 17. Output Valid Delay TimingFigure 18. Input Setup and Hold TimingFig

viiiAMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 41. SMI/SMIACT Timing . . . . . . . . . . . . . . . . . . . . . . . . .

70AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 20. Reset and Configuration TimingTxCLK RESETTxt36INIT, FLUSH, FRCMC1.5

7118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 21. TCK WaveformFigure 22. TRST TimingFigure 23. Test Signal Timing

72AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION11 Timing DiagramsFigure 24. STPCLK Timing (Stop Grant state)Figure 25. Trans

7318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 26. Invalidation to Non-Modified L1 Cache LineFigure 27. Invalidation

74AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 28. Single Read due to CACHE Inactive (No Wait State)Figure 29. Single

7518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 30. Single Write due to KEN Inactive (No Wait State)Figure 31. Single

76AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 32. Burst Read (No Wait State)Figure 33. Burst Read (One Wait State)Cl

7718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 34. Burst Write (One Wait State)Figure 35. BOFF TimingClockAddressData

78AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 36. Locked CycleFigure 37. HOLD/HLDA TimingClockAddressDataADSBRDYCACH

7918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 38. AHOLD RestrictionsFigure 39. Special CycleAHOLD may not change dur

ix18522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONList of TablesTable 1. Input Pins. . . . . . . . . . . . . . . . . . . . . . . .

80AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATIONFigure 40. Interrupt AcknowledgeFigure 41. SMI/SMIACT TimingStart blankend bl

8118522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONFigure 42. Split Cycle (Misaligned Locked cycle)ClockAddressDataADSBRDYCACHEW/R

82AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION12 Package Thermal SpecificationsThe AMD-K5 processor is specified for operation

8318522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATIONTable 28. Model 0 Maximum TA in °CHeat SinkAirflow of 0 (0) ft/min. (m/sec)PR751P

84AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION13 Physical DimensionsFigure 43. 296-Pin Ceramic Staggered Pin Grid Array (SPGA

8518522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION14 Pin Description Diagram (Model 0)Figure 44. AMD-K5 Model 0 Processor Pin-Sid

86AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION15 Pin Designations (Model 0)Functional GroupingAddress Data Control Test NC VccV

8718522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION16 Pin Description Diagram (Models 1 and 2)Figure 45. AMD-K5 Models 1 and 2 Pro

88AMD-K5 Processor Data Sheet 18522F/0—Jan1997PRELIMINARY INFORMATION17 Pin Designations (Models 1 and 2)Functional GroupingAddress Data Control Test

8918522F/0—Jan1997 AMD-K5 Processor Data SheetPRELIMINARY INFORMATION