AMD Duron Manual de usuario descargar pdf (Pagina 36)

24 Electrical Data Chapter 6

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

Figure 9. SYSCLK Waveform

Low Time 4 ns

Fall Time 500 ps 4

Rise Time 500 ps 3

Period Stability

± 300 ps

Table 11. SYSCLK and SYSCLK# AC Characteristics (continued)

Symbol Description Min Max Units Notes

Notes:

1. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track

the jitter. The –20 dB attenuation point, as measured into a 10-pF or 20-pF load must be less than 500 kHz.

2. Circuitry driving the SYSCLK and SYSCLK# inputs may purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock

generators). In no cases can the period violate the minimum specification above. SYSCLK and SYSCLK# inputs may vary from

100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz.

3. Measured from 0.5 V to VCC_CORE

4. Measured from VCC_CORE to 0.5 V

Threshold-AC

CROSS

–V

Threshold-AC

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AMD Duron Manual de usuario Pagina 36