Amd Geode LX [email protected] Manual de usuario Pagina 210
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Valorado. / 5. Basado en revisión del cliente
210 AMD Geode™ LX Processors Data Book
GeodeLink™ Memory Controller
33234H
6.1 GeodeLink™ Memory Controller
The GeodeLink™ Memory Controller (GLMC) module sup-
ports the Unified Memory Architecture (UMA) of the
AMD Geode™ LX processor and controls a 64-bit DDR
SDRAM interface without any external buffering. The inter-
nal block diagram of the GLMC is shown in Figure 6-2.
The SDRAM memory array contains both the main system
memory and the graphics frame buffer. Up to four module
banks of SDRAM are supported. Each module bank can
have two or four component banks depending on the mem-
ory size and organization. The maximum configuration is
four module banks with four component banks, each pro-
viding a total of 16 open banks with the maximum memory
size supported being 2 GB.
The GLMC handles multiple requests for memory data
from the CPU Core, the Graphics Processor, the Display
Controller, and the external PCI bus via the GeodeLink
Interface Units (GLIUs). The GLMC contains extensive
buffering logic that helps minimize contention for memory
bandwidth between the various requests.
Figure 6-2. GLMC Block Diagram
Adrs/Ctl
Gen
Req Req
Refresh
Arbiter
Data
Control
SDRAM IF
MSR
Registers
W_DATA
Write
Response
MSR
Rd Resp
Data Path
RAS
CAS
WE
CKE
MA
BA
CS
DQ
DQM
DQS
Bank/
Page
Logic
Buf Buf
R_DATA
MemRd
Response
GLUI0
Request
Packet
GLUI0
Write
Packet
GLUI0
Response
Packet
Write
Buf
Write
Buf
Write
Buf
Capture/
Resync
- AMD Geode™ LX Processors 1
- Data Book 1
- Contents 3
- List of Figures 5
- List of Tables 10
- 1.0Overview 11
- 1.2 Features 12
- Overview 14
- 2.0Architecture Overview 15
- 2.1.5 Floating Point Unit 16
- 2.1.2 Memory Management Unit 16
- 2.1.3 Cache and TLB Subsystem 16
- 2.1.4 Bus Controller Unit 16
- 2.5 Graphics Processor 17
- 2.6 Display Controller 18
- 2.7 Video Processor 18
- 2.8 Video Input Port 18
- 2.9 GeodeLink™ PCI Bridge 18
- 2.10 Security Block 19
- Architecture Overview 20
- 3.0Signal Definitions 21
- 3.1 Buffer Types 23
- 3.2 Bootstrap Options 24
- 3.3 Ball Assignments 24
- AMD Geode™ 25
- LX Processor 25
- Signal Definitions 26
- 3.4 Signal Descriptions 33
- 3.4.2 PLL Interface Signals 34
- 3.4.5 PCI Interface Signals 37
- 3.4.8 VIP Interface Signals 41
- 4.0GeodeLink™ Interface Unit 45
- 4.1.1 Port Address 46
- 4.1.3 Memory and I/O Mapping 47
- Table 4-2. MSR Mapping 47
- P2D Descriptor 50
- GLIU Register Descriptions 51
- _MSR_CAP Register Map 55
- _MSR_CAP Bit Descriptions 55
- _MSR_CONFIG Register Map 55
- _MSR_CONFIG Bit Descriptions 55
- _MSR_SMI Register Map 56
- _MSR_SMI Bit Descriptions 56
- _MSR_ERROR Register Map 57
- _MSR_ERROR Bit Descriptions 57
- _MSR_PM Register Map 59
- 4.2.2 GLIU Specific Registers 60
- _MSR_PM Bit Descriptions 60
- COH Register Map 60
- COH Bit Descriptions 60
- PAE Register Map 61
- PAE Bit Descriptions 61
- ARB Register Map 62
- ARB Bit Descriptions 62
- ASMI Register Map 62
- ASMI Bit Descriptions 63
- AERR Register Map 64
- AERR Bit Descriptions 64
- PHY_CAP Register Map 65
- PHY_CAP Bit Descriptions 65
- NOUT_RESP Register Map 66
- NOUT_RESP Bit Descriptions 66
- NOUT_WDATA Register Map 67
- NOUT_WDATA Bit Descriptions 67
- SLAVE_ONLY Register Map 67
- SLAVE_ONLY Bit Descriptions 67
- WHO AM I Register Map 68
- WHO AM I Bit Descriptions 68
- GLIU_SLV Register Map 69
- GLIU_SLV Bit Descriptions 69
- ARB2 Register Map 70
- ARB2 Bit Descriptions 70
- RQ_COMPARE_VAL[0:3] Register 74
- DA_COMPARE_MASK_HI[0:3]) 79
- P2D_BM Register Map 80
- P2D_BM Bit Descriptions 80
- P2D_BMO Register Map 81
- P2D_BMO Bit Descriptions 81
- P2D_R Register Map 82
- P2D_R Bit Descriptions 82
- P2D_RO Register Map 83
- P2D_RO Bit Descriptions 83
- P2D_SC Register Map 84
- P2D_SC Bit Descriptions 84
- SPARE_MSR[x] Register Map 85
- SPARE_MSR[x] Bit Descriptions 85
- 4.2.6 I/O Descriptors 86
- IOD_BM[x] Register Map 86
- IOD_BM[x] Bit Descriptions 86
- IOD_SC[x] Register Map 87
- IOD_SC[x] Bit Descriptions 87
- 5.0CPU Core 89
- 5.2 Instruction Set Overview 90
- 5.3 Application Register Set 91
- 5.3.2 Segment Registers 92
- 5.3.4 EFLAGS Register 93
- Table 5-4. EFLAGS Register 93
- 5.4 System Register Set 94
- 5.4.1 Control Registers 95
- CPU Core 96
- GLD_MSR_CAP Register Map 108
- GLD_MSR_CAP Bit Descriptions 108
- GLD_MSR_CONFIG Register Map 108
- TSC_MSR Bit Descriptions 110
- PERF_CNT0_MSR Register Map 110
- 5.5.2 CPU Core Specific MSRs 110
- TSC_MSR Register Map 110
- PERF_CNT1_MSR Register Map 111
- SYS_CS_MSR Register Map 112
- SYS_CS_MSR Bit Descriptions 112
- SYS_SP_MSR Register Map 113
- SYS_SP_MSR Bit Descriptions 113
- SYS_IP_MSR Register Map 113
- SYS_IP_MSR Bit Descriptions 113
- PERF_SEL0_MSR Register Map 114
- PERF_SEL1_MSR Register Map 114
- IF_CONFIG_MSR Register Map 115
- IF_TEST_ADDR_MSR Register Map 118
- IF_SEQCOUNT_MSR Register Map 122
- IF_BIST_MSR Register Map 123
- IF_BIST_MSR Bit Descriptions 123
- XC_CONFIG_MSR Register Map 124
- XC_MODE_MSR Register Map 125
- XC_MODE_MSR Bit Descriptions 125
- XC_HIST_MSR Register Map 126
- XC_HIST_MSR Bit Descriptions 126
- XC_UADDR_MSR Register Map 127
- XC_UADDR_MSR Bit Descriptions 127
- ID_CONFIG_MSR Register Map 127
- SMM_CTL_MSR Register Map 128
- SMM_CTL_MSR Bit Descriptions 128
- DMI Control Register Map 129
- TEMPx_MSR Register Map 130
- TEMPx_MSR Bit Descriptions 130
- SMM_HDR_MSR Register Map 132
- SMM_HDR_MSR Bit Descriptions 132
- DMM_HDR_MSR Register Map 133
- DMM_HDR_MSR Bit Descriptions 133
- DR1_DR0_MSR Register Map 135
- DR1_DR0_MSR Bit Descriptions 135
- DR3_DR2_MSR Register Map 135
- DR2_DR3_MSR Bit Descriptions 135
- DR7_DR6_MSR Register Map 136
- DR7_DR6_MSR Bit Descriptions 136
- XDR1_XDR0_MSR Register Map 137
- XDR3_XDR2_MSR Register Map 137
- XDR5_XDR4_MSR Register Map 138
- XDR7_XDR6_MSR Register Map 138
- XDR9_XDR8_MSR Register Map 140
- XDR11_XDR10_MSR Register Map 141
- EX_IP_MSR Register Map 141
- EX_IP_MSR Bit Descriptions 141
- WB_IP_MSR Register Map 142
- WB_IP_MSR Bit Descriptions 142
- EX_LIP_MSR Register Map 142
- EX_LIP_MSR Bit Descriptions 142
- WB_LIP_MSR Register Map 143
- WB_LIP_MSR Bit Descriptions 143
- C1_C0_LIP_MSR Register Map 143
- C3_C2_LIP_MSR Register Map 144
- FPENV_CS_MSR Register Map 144
- FPENV_CS_MSR Bit Descriptions 144
- FPENV_IP_MSR Register Map 145
- FPENV_IP_MSR Bit Descriptions 145
- FPENV_DS_MSR Register Map 145
- FPENV_DS_MSR Bit Descriptions 145
- FPENV_DP_MSR Register Map 146
- FPENV_DP_MSR Bit Descriptions 146
- FPENV_OP_MSR Register Map 146
- FPENV_OP_MSR Bit Descriptions 146
- AC_CONFIG_MSR Register Map 147
- EFLAG_MSR Register Map 149
- EFLAG_MSR Bit Descriptions 149
- IM_CONFIG_MSR Register Map 150
- IC_INDEX_MSR Register Map 152
- IC_DATA_MSR Register Map 152
- IC_DATA_MSR Bit Descriptions 152
- IC_TAG_MSR MSR Register Map 153
- IC_TAG_MSR Bit Descriptions 153
- IC_TAG_I_MSR Register Map 154
- IC_TAG_I_MSR Bit Descriptions 154
- L0_IC_DATA_MSR Register Map 154
- L0_IC_TAG_I_MSR Register Map 154
- ITB_INDEX_MSR Register Map 155
- ITB_LRU_MSR Register Map 156
- ITB_LRU_MSR Bit Descriptions 156
- IM_BIST_TAG_MSR Register Map 158
- IM_BIST_DATA_MSR Register Map 158
- DM_CONFIG0_MSR Register Map 159
- DM_CONFIG1_MSR Register Map 162
- DM_PFLOCK_MSR Register Map 163
- RCONF_BYPASS_MSR Register Map 165
- RCONF_A0_BF_MSR Register Map 165
- RCONF_C0_DF_MSR Register Map 166
- RCONF_E0_FF_MSR Register Map 166
- RCONF_SMM_MSR Register Map 167
- RCONF_DMM_MSR Register Map 168
- RCONFx_MSR Register Map 169
- RCONFx_MSR Bit Descriptions 169
- DC_INDEX_MSR Register Map 172
- DC_DATA_MSR Register Map 173
- DC_DATA_MSR Bit Descriptions 173
- DC_TAG_MSR Register Map 173
- DC_TAG_MSR Bit Descriptions 173
- DC_TAG_I_MSR Register Map 174
- SNOOP_MSR Register Map 175
- SNOOP_MSR Bit Descriptions 175
- L1DTLB_INDEX_MSR Register Map 175
- L1DTLB_LRU_MSR Register Map 176
- L1DTLB_ENTRY_MSR Register Map 177
- L2TLB_INDEX_MSR Register Map 178
- L2TLB_LRU_MSR Register Map 179
- L2TLB_ENTRY_MSR Register Map 180
- DM_BIST_MSR Register Map 182
- DM_BIST_MSR Bit Descriptions 182
- BC_CONFIG0_MSR Register Map 183
- RSVD_STS_MSR Bit Descriptions 185
- MSR_LOCK_MSR Register Map 185
- RTSC_MSR Register Map 186
- RTSC_MSR Bit Descriptions 186
- RTSC_TSC_MSR Register Map 186
- RTSC_TSC_MSR Bit Descriptions 186
- L2_CONFIG_MSR Register Map 187
- L2_STATUS_MSR Register Map 188
- L2_INDEX_MSR Register Map 188
- L2_INDEX_MSR Bit Descriptions 188
- L2_DATA_MSR Register Map 189
- L2_DATA_MSR Bit Descriptions 189
- L2_TAG_MSR Register Map 189
- L2_TAG_MSR Bit Descriptions 189
- L2_TAG_I_MSR Register Map 190
- L2_BIST_MSR Register Map 190
- L2_BIST_MSR Bit Descriptions 190
- PMODE_MSR Register Map 193
- PMODE_MSR Bit Descriptions 193
- BXDR1_BXDR0_MSR Register Map 194
- BXDR3_BXDR2_MSR Register Map 194
- BXDR6_BXDR7_MSR Register Map 195
- BDRx_MSR Register Map 197
- BDRx_MSR Bit Descriptions 197
- BDR6_MSR Register Map 198
- BDR6_MSR Bit Descriptions 198
- BDR7_MSR Register Map 198
- BDR7_MSR Bit Descriptions 198
- FP_MODE_MSR Register Map 202
- FP_MODE_MSR Bit Descriptions 202
- FPU_CW_MSR Register Map 203
- FPU_CW_MSR Bit Descriptions 203
- FPU_SW_MSR Register Map 203
- FPU_SW_MSR Bit Descriptions 203
- FPU_TW_MSR Register Map 203
- FPU_TW_MSR Bit Descriptions 204
- FPU_BUSY_MSR Register Map 204
- FPU_BUSY_MSR Bit Descriptions 204
- FPU_MAP_MSR Register Map 204
- FPU_MAP_MSR Bit Descriptions 204
- FPU_MRx_MSR Register Map 205
- FPU_MRx_MSR Bit Descriptions 205
- FPU_ERx_MSR Register Map 206
- FPU_ERx_MSR Bit Descriptions 206
- CPUIDx_MSR Register Map 208
- CPUIDx_MSR Bit Descriptions 208
- 6.0Integrated Functions 209
- GeodeLink™ Memory Controller 210
- Figure 6-7. Request Pipeline 215
- Figure 6-8. DDR Reads 216
- Figure 6-9. DDR Writes 217
- 6.1.2 Power Control 218
- GLD_MSR_CAP Register 220
- GLD_MSR_ERROR Register Map 221
- GLD_MSR_PM Register Map 222
- GLD_MSR_PM Bit Descriptions 222
- 6.2.2 GLMC Specific MSRs 223
- MC_CF_BANK01 Register Map 223
- MC_CF_BANK01 Bit Descriptions 223
- MC_CF_BANK23 Register Map 223
- MC_CF_BANK23 Bit Descriptions 223
- MC_CF_BANK45 Register Map 224
- MC_CF_BANK45 Bit Descriptions 224
- MC_CF_BANK67 Register Map 224
- MC_CF_BANK67 Bit Descriptions 224
- MC_CF_BANK89 Register Map 225
- MC_CF_BANK89 Bit Descriptions 225
- MC_CF_BANKAB Register Map 225
- MC_CF_BANKAB Bit Descriptions 225
- MC_CF_BANKCD Register Map 226
- MC_CF_BANKCD Bit Descriptions 226
- MC_CF_BANKEF Register Map 226
- MC_CF_BANKEF Bit Descriptions 226
- MC_CF07_DATA Register Map 227
- MC_CF07_DATA Bit Descriptions 227
- MC_CF8F_DATA Register Map 229
- MC_CF8F_DATA Bit Descriptions 230
- MC_CF1017_DATA Register Map 231
- MC_CFPERF_CNT1 Register Map 232
- MC_PERFCNT2 Register Map 233
- MC_PERFCNT2 Bit Descriptions 233
- MC_CFCLK_DBUG Register Map 233
- MC_CFPG_OPEN Register Map 235
- MC_CFPG_OPEN Bit Descriptions 235
- MC_CF_PMCTR Register Map 236
- MC_CF_PMCTR Bit Descriptions 236
- 6.3 Graphics Processor 237
- Graphics Processor 238
- 6.3.1 Command Buffer 239
- 6.3.2 Channel 3 241
- Table 6-12. Bit Descriptions 241
- 6.3.3 BLT Operation 245
- 6.3.4 Vector Operation 246
- 6.3.5 Pipelined Operation 246
- 6.3.6 Pattern Generation 246
- 6.3.9 Destination Data 251
- (GP_DST_OFFSET) 254
- (GP_SRC_OFFSET) 254
- (GP_BASE_OFFSET) 255
- 00000000h Page 272 255
- GLD_MSR_SMI Register Map 257
- GLD_MSR_SMI Bit Descriptions 257
- GP_DST_OFFSET Register Map 259
- GP_SRC_OFFSET Register Map 259
- GP_VEC_ERR Register Map 260
- GP_VEC_ERR Bit Description 260
- GP_STRIDE Register Map 260
- GP_STRIDE Bit Descriptions 261
- GP_WID_HEIGHT Register Map 261
- GP_VEC_LEN Register Map 261
- GP_VEC_LEN Bit Descriptions 261
- GP_SRC_COLOR_FG Register Map 262
- GP_SRC_COLOR_BG Register Map 263
- GP_PAT_COLOR_x Register Map 264
- GP_PAT_DATA_x Register Map 265
- GP_RASTER_MODE Register Map 265
- 01: Mono pattern 266
- GP_VECTOR_MODE Register Map 267
- GP_BLT_MODE Register Map 268
- GP_BLT_MODE Bit Descriptions 268
- GP_BLT_STATUS Register Map 269
- GP_HST_SRC Register Map 269
- GP_HST_SRC Bit Descriptions 270
- GP_BASE_OFFSET Register Map 270
- GP_CMD_TOP Register Map 270
- GP_CMD_TOP Bit Descriptions 270
- GP_CMD_BOT Register Map 271
- GP_CMD_BOT Bit Descriptions 271
- GP_CMD_READ Register Map 271
- GP_CMD_READ Bit Descriptions 271
- GP_CMD_WRITE Register Map 272
- GP_CMD_WRITE Bit Descriptions 272
- GP_CH3_OFFSET Register Map 272
- GP_CH3_MODE_STR Register Map 273
- GP_CH3_WIDHI Register Map 275
- GP_CH3_WIDHI Bit Descriptions 275
- GP_CH3_HSRC Register Map 275
- GP_CH3_HSRC Bit Descriptions 275
- GP_INT_CNTRL Register Map 277
- GP_INT_CNTRL Bit Descriptions 277
- 6.5 Display Controller 278
- Display Controller 280
- 6.5.1 GUI Functional Overview 281
- Table 6-32. Display Modes 281
- Table 6-36. Video Bandwidth 286
- Table 6-39. VGA Text Modes 288
- 6.5.6 Graphics Scaler/Filter 293
- (DC_VID_Y_ST_OFFSET) 301
- (DC_VID_U_ST_OFFSET) 301
- (DC_VID_V_ST_OFFSET) 301
- (DC_GLIU0_MEM_OFFSET) 301
- (DC_VID_EVEN_Y_ST_OFFSET) 302
- (DC_VID_EVEN_U_ST_OFFSET) 302
- (DC_VID_EVEN_V_ST_OFFSET) 302
- SPARE_MSR Register Map 311
- SPARE_MSR Bit Descriptions 311
- DC_RAM_CTL_MSR Register Map 311
- DC_UNLOCK Register Map 312
- DC_UNLOCK Bit Descriptions 313
- DC_GENERAL_CFG Register Map 314
- , or 4 KB 315
- 3VIDE Video Enable 316
- DC_DISPLAY_CFG Register Map 317
- DC_ARB_CFG Register Map 319
- DC_ARB_CFG Bit Descriptions 319
- DC_FB_ST_OFFSET 321
- DC_CB_ST_OFFSET Register Map 322
- DC_DV_TOP Register Map 324
- DC_DV_TOP Bit Descriptions 325
- DC_LINE_SIZE Register Map 325
- DC_LINE_SIZE Bit Descriptions 325
- DC_GFX_PITCH Register Map 326
- DC_GFX_PITCH Bit Descriptions 326
- DC_VID_YUV_PITCH Register Map 326
- 6.6.5 Timing Registers 327
- RSVD H_TOTAL RSVD H_ACTIVE 328
- DC_H_SYNC_TIMING Register Map 329
- RSVD V_TOTAL RSVD V_ACTIVE 330
- DC_V_SYNC_TIMING Register Map 331
- DC_FB_ACTIVE Register Map 332
- DC_FB_ACTIVE Bit Descriptions 332
- DC_CURSOR_X Register Map 332
- DC_CURSOR_X Bit Descriptions 332
- DC_CURSOR_Y Register Map 333
- DC_CURSOR_Y Bit Descriptions 333
- 20h[27:0]) has not 334
- DC_PAL_ADDRESS Register Map 335
- DC_PAL_DATA Register Map 336
- DC_PAL_DATA Bit Descriptions 336
- DC_DFIFO_DIAG Register Map 336
- DC_CFIFO_DIAG Register Map 337
- 6.6.8 Video Downscaling 338
- DC_VID_DS_DELTA Register Map 338
- 6.6.9 GLIU Control Registers 339
- DC_DV_CTL Register Map 339
- DV_CTL Bit Descriptions 339
- DC_DV_ACCESS Register Map 340
- DC_DV_ACCESS Bit Descriptions 340
- DC_GFX_SCALE Register Map 341
- DC_GFX_SCALE Bit Descriptions 341
- DC_IRQ_FILT_CTL Register Map 342
- DC_FILT_COEFF1 Register Map 343
- 6.6.11 VBI Control Registers 344
- DC_FILT_COEFF2 Register Map 344
- DC_VBI_EVEN_CTL Register Map 344
- DC_VBI_ODD_CTL Register Map 345
- DC_VBI_HOR Register Map 345
- DC_VBI_HOR Bit Descriptions 345
- DC_VBI_LN_ODD Register Map 346
- DC_VBI_LN_EVEN Register Map 346
- DC_VBI_PITCH Register Map 347
- DC_CLR_KEY Register Map 347
- DC_CLR_KEY Bit Descriptions 347
- DC_CLR_KEY_MASK Register Map 348
- DC_CLR_KEY_X Register Map 348
- DC_CLR_KEY_Y Register Map 348
- DC_CLR_KEY_Y Bit Descriptions 349
- DC_IRQ Register Map 349
- DC_IRQ Bit Descriptions 349
- DC_GENLK_CTL Register Map 350
- DC_GENLK_CTL Bit Descriptions 350
- RSVD OFFSET 351
- VGA_CONFIG Register Map 355
- VGA_CONFIG Bit Descriptions 355
- VGA_STATUS Register Map 355
- VGA_STATUS Bit Descriptions 355
- Table 6-52. Font Table 360
- 00h Page 369 362
- 6.6.19.23 Underline Location 369
- 6.6.22 Video DAC Registers 382
- 6.7 Video Processor 388
- Video Processor 389
- Flat Panel 389
- Video Processor Module 389
- 6.7.3 X and Y Upscaler 393
- 6.7.4 Color Space Converter 393
- 6.7.5 Video Overlay 394
- Use video value 396
- 6.7.6 Video Output Port 398
- Table 6-61. VOP Mode 401
- Table 6-62. SAV/EAV Sequence 402
- Table 6-64. SAV VIP Flags 404
- Table 6-65. VOP Clock Rate 404
- Disable Feature 410
- 6.7.8 VP Resolution Table 411
- 6.7.9 Display RGB Modes 411
- Table 6-68. Display RGB Modes 411
- MSR_DIAG_VP Register Map 419
- MSR_DIAG_VP Bit Descriptions 419
- MSR_PADSEL Register Map 420
- MSR_PADSEL Bit Descriptions 420
- VCFG Register Map 421
- VCFG Bit Descriptions 421
- DCFG Register Map 422
- DCFG Bit Descriptions 423
- VX Register Map 424
- VX Bit Descriptions 424
- VY Register Map 425
- VY Bit Descriptions 425
- SCL Register Map 425
- SCL Bit Descriptions 425
- VCK Register Map 426
- VCK Bit Descriptions 426
- VCM Register Map 427
- VCM Bit Descriptions 427
- PAR Register Map 428
- PAR Bit Descriptions 428
- PDR Register Map 428
- PDR Bit Descriptions 428
- SLR Register Map 429
- SLR Bit Descriptions 429
- MISC Register Map 430
- MISC Bit Descriptions 430
- VYS Register Map 431
- VYS Bit Descriptions 431
- VXS Register Map 431
- VXS Bit Descriptions 432
- VDC Register Map 432
- VDC Bit Descriptions 432
- CRC Register Map 433
- CRC Bit Descriptions 433
- CRC32 Register Map 434
- CRC32 Bit Descriptions 434
- VDE Register Map 434
- VDE Bit Descriptions 434
- CCK Register Map 436
- CCK Bit Descriptions 436
- CCM Register Map 437
- CCM Bit Descriptions 437
- CC1 Register Map 437
- CC1 Bit Descriptions 437
- CC2 Register Map 438
- CC2 Bit Descriptions 438
- A1X Register Map 438
- A1X Bit Descriptions 438
- A1Y Register Map 439
- A1Y Bit Descriptions 439
- A1C Register Map 439
- A1C Bit Descriptions 440
- A1T Register Map 440
- A1T Bit Descriptions 441
- A2X Register Map 441
- A2X Bit Descriptions 441
- A2Y Register Map 442
- A2Y Bit Descriptions 442
- A2C Register Map 442
- A2C Bit Descriptions 443
- A2T Register Map 443
- A2T Bit Descriptions 443
- A3X Register Map 444
- A3X Bit Descriptions 444
- A3Y Register Map 445
- A3Y Bit Descriptions 445
- A3C Register Map 445
- A3C Bit Descriptions 446
- A3T Register Map 446
- A3T Bit Descriptions 446
- VRR Register Map 447
- VRR Bit Descriptions 447
- AWT Register Map 448
- AWT Bit Descriptions 448
- VTM Register Map 448
- VTM Bit Descriptions 448
- VYE Register Map 449
- VYE Bit Descriptions 449
- A1YE Register Map 449
- A1YE Bit Descriptions 449
- A2YE Register Map 450
- A2YE Bit Descriptions 450
- A3YE Register Map 450
- A3YE Bit Descriptions 450
- VCR Register Map 451
- VCR Bit Descriptions 451
- PT1 Register Map 451
- PT1 Bit Descriptions 451
- PT2 Register Map 453
- PT2 Bit Descriptions 453
- PM Register Map 454
- PM Bit Descriptions 454
- DFC Register Map 456
- DFC Bit Descriptions 456
- DCA Register Map 457
- DCA Bit Descriptions 457
- DMD Register Map 458
- DMD Bit Descriptions 458
- Register Map 459
- Bit Descriptions 459
- Bit Descriptions (Continued) 460
- 6.9 Video Input Port 462
- 6.9.2 VIP Block Descriptions 463
- Video Input Port 464
- 6.9.3 Functional Description 465
- 6.9.4 VIP Operation Modes 465
- (simplified BT.656) 466
- Table 6-73. SAV/EAV Sequence 466
- 6.9.6 Message Passing Mode 470
- 6.9.7 Data Streaming Mode 470
- 6.9.8 BT.601 Mode 471
- 6.9.10 Software Model 475
- 6.9.11 Bob and Weave 480
- 6.9.12 VIP Interrupts 480
- 6.9.13 VIP Input Video Status 481
- VIP_CTL_REG1 Register Map 488
- VIP_CTL_REG1 Bit Descriptions 488
- VIP_CTL_REG2 Register Map 490
- VIP_CTL_REG2 Bit Descriptions 490
- ) and FIFO 491
- 100-111: 0 491
- VIP_STATUS Register Map 492
- VIP_STATUS Bit Descriptions 492
- VIP_INT Register Map 494
- VIP_INT Bit Descriptions 494
- VIP_CUR_TAR Register Map 495
- VIP_MAX_ADDR Register Map 495
- VIP_MAX_ADDR Bit Descriptions 495
- VIP_CONTRL_REG3 Register Map 498
- (VIP_TASK_A_V_OFFSET) 499
- even lines will also 499
- TASK_B_V_OFFSET_START_ODD 503
- TASK_B_U_OFFSET) 504
- VIP_ANC_MSG_SIZE Register Map 505
- VIP_FIFO_DATA Register Map 507
- 6.11 Security Block 510
- 6.11.2 Functional Description 511
- Security Block 512
- GLD_MSR_CTRL Register Map 519
- GLD_MSR_CTRL Bit Descriptions 519
- SB_CTL_A Register Map 520
- SB_CTL_B Register Map 521
- SB_AES_INT Register Map 522
- SB_SOURCE_A Register Map 522
- SB_DEST_A Register Map 523
- SB_LENGTH_A Register Map 523
- SB_SOURCE_B Register Map 524
- SB_DEST_B Register Map 524
- SB_LENGTH_B Register Map 525
- SB_WKEY_1 Register Map 526
- SB_WKEY_1 Bit Descriptions 526
- SB_WKEY_2 Register Map 526
- SB_WKEY_2 Bit Descriptions 526
- SB_WKEY_3 Register Map 527
- SB_WKEY_3 Bit Descriptions 527
- SB_CBC_IV_0 Register Map 527
- SB_CBC_IV_0 Bit Descriptions 527
- SB_RANDOM_NUM Register Map 529
- SB_EEPROM_COMM Register Map 530
- SB_EEPROM_ADDR Register Map 531
- SB_EEPROM_DATA Register Map 531
- 6.13.1 TAP Controller 533
- GeodeLink™ Control Processor 534
- 6.13.2 Reset Logic 535
- 6.13.3 Clock Control 535
- Table 6-83. GIO_PCI Outputs 537
- GLCP_GLB_PM Register Map 547
- GLCP_GLB_PM Bit Descriptions 547
- GLCP_PROCSTAT Register Map 548
- GLCP_DOWSER Register Map 549
- GLCP_DOWSER Bit Descriptions 549
- GLCP_CLKOFF Register Map 551
- GLCP_CLKOFF Bit Descriptions 551
- GLCP_CLKACTIVE Register Map 552
- GLCP_CLKDISABLE Register Map 553
- GLCP_CLK4ACK Register Map 553
- GLCP_SYS_RSTPLL Register Map 554
- GLCP_DOTPLL Register Map 557
- GLCP_DOTPLL Bit Descriptions 558
- GLCP_DBGCLKCTL Register Map 559
- GLCP_CHIP_REVID Register Map 559
- GLCP_CNT Register Map 560
- GLCP_CNT Bit Descriptions 560
- GLCP_TH_SD Register Map 561
- GLCP_TH_SD Bit Descriptions 561
- GLCP_TH_SF Register Map 561
- GLCP_TH_SF Bit Descriptions 561
- 6.14.3 GLCP IGNNE I/Os 562
- GLCP_TH_OD Register Map 562
- GLCP_TH_OD Bit Descriptions 562
- GLCP_DAC Register Map 563
- GLCP_DAC Bit Descriptions 563
- MSR_A20M Register Map 564
- MSR_A20M Bit Descriptions 564
- MSR_INIT Register Map 564
- MSR_INIT Bit Descriptions 564
- MSR_INTAX Register Map 565
- MSR_INTAX Bit Descriptions 565
- 6.15 GeodeLink™ PCI Bridge 566
- GeodeLink™ PCI Bridge 567
- AMD Geode™ LX Processor 568
- 6.15.6 Exception Handling 571
- GLPCI_CTRL Register Map 578
- GLPCI_CTRL Bit Descriptions 578
- GLPCI_ARB Register Map 581
- GLPCI_ARB Bit Definitions 582
- GLPCI_PBUS Register Map 584
- GLPCI_PBUS Bit Descriptions 584
- GLPCI_REN Register Map 584
- GLPCI_REN Bit Descriptions 585
- GLPCI_A0 Register Map 585
- GLPCI_A0 Bit Descriptions 586
- Table 6-93. Region Properties 586
- GLPCI_C0 Register Map 586
- GLPCI_C0 Bit Descriptions 586
- GLPCI_E0 Register Map 587
- GLPCI_E0 Bit Descriptions 587
- GLPCI_R0 Register Map 588
- GLPCI_R0 Bit Descriptions 588
- GLPCI_R1 Register Map 589
- GLPCI_R1 Bit Descriptions 589
- GLPCI_R2 Register Map 590
- GLPCI_R2 Bit Descriptions 590
- GLPCI_R3 Register Map 591
- GLPCI_R3 Bit Descriptions 591
- GLPCI_R4 Register Map 592
- GLPCI_R4 Bit Descriptions 592
- GLPCI_R5 Register Map 593
- GLPCI_R5 Bit Descriptions 593
- GLPCI_EXT_MSR Register Map 594
- GLPCI Spare 595
- GLPCI Spare Bit Descriptions 595
- GLPCI_GPIO Register Map 596
- 7.0Electrical Specifications 597
- 7.3 Operating Conditions 598
- 7.4 DC Current 599
- Figure 7-1. V 600
- Power Split 600
- Electrical Specifications 601
- MEMDDR2ON 601
- 7.5 DC Characteristics 604
- 7.6 AC Characteristics 607
- 8.0Instruction Set 619
- 8.1.1 Prefix (Optional) 620
- Table 8-2. Instruction Fields 620
- 8.1.2 Opcode 621
- Table 8-4. w Field Encoding 621
- Table 8-5. d Field Encoding 621
- Table 8-6. s Field Encoding 621
- Table 8-7. eee Field Encoding 622
- 8.1.4 reg Field 624
- Table 8-10. reg Field 624
- Table 8-13. ss Field Encoding 625
- Instruction Set 626
- 8.2 CPUID Instruction Set 627
- 8.2.2 Extended CPUID Levels 629
- 8.3.1 Opcodes 633
- 8.3.2 Clock Counts 633
- 8.3.3 Flags 633
- × TOS; then pop TOS 1/10 668
- × M.SI 2/11 668
- × M.WI 2/11 668
- 9.0Package Specifications 675
- Package Specifications 676
- A.1 Order Information 677
- Table A-2. Revision History 679
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